ARTICLE AD BOX
I am writing an embedded OS to run on Risc-V. As part of that, I'm implementing a FIFO for UART buffering using the classic single consumer/single producer module. The class looks like this:
template <typename T, size_t BufferSize = 1024> class P1C1 { volatile T _buffer[BufferSize]; volatile unsigned _producerIndex = 0, _consumerIndex = 0; ...(source code).
The problem is that when instantiated as a global, this gets placed in the BSS section, which means that my system spends over 2ms zeroing out a buffer that is never going to be read before it's written.
And I know that 2ms does not sound like a lot, but when you run this in a Verilog simulator, those 2ms of execution time turn into over 30 minutes of simulation time, waiting for the system to load just so you can debug what you're really after.
Is there a way to specify "this is a global variable, but do not initialize it at all"?
